It is known to use an analogue chip to recover, in digital format, analogue data which is recorded on a medium, such as a tape. Referring to FIG. 1 of the drawings, which illustrates a simplified version of such analogue chip, such a data recovery circuit generally comprises a variable gain amplifier (VGA) 100, which receives analogue signal 102 from a tape (not shown), a filter 104 to smooth the analogue waveform, an analogue-to-digital converter (ADC) 106 for converting, the smoothed analogue waveform 108 into a 6-bit digital signal, a digital signal processing module 110, a Viterbi decoder 112 to produce a 6-bit output, and an RRL decoder 114, which produces 4-bit output data.
The output from the RLL decoder 114 is then input to an error correction circuit (not shown). In general, the number of errors which known error correction circuits can detect and/or correct is dependent on the number of parity symbols which are added to the data. An error in a code word has two unknown quantities, namely its location and the amount by which a symbol is incorrect. If, for example, four parity symbols are added to each code word, a conventional error detection/correction circuit can deal with four unknown quantities, i.e. two errors. If, however, the location of an error is known, there is only one unknown quantity, so the circuit can handle up to four errors in a code word if their locations are known. The term used to describe an error whose location is known is an “erasure”, and, in general, conventional error correction circuits can correct twice as many erasures as errors.
When analogue data is read from a tape (not shown), it is common for errors to occur, which result in bad data being read. For example, the tape may flap away from the tape head (“drop-out”) or the temperature of a magneto resistive head may suddenly change, causing a thermal asperity. A change in the head temperature causes a change in the head resistance resulting in a DC shift in the analogue signal. The temperature of the head can change suddenly when a piece of dust or debris on the tape hits the head. The dust or debris either heats the head due to friction, or cools the head by conduction. The tape channel is AC coupled to the head so, after a certain amount of time (dependent upon the magnitude of the DC shift), the signal comes back into range. However, in the meantime, the DC shift can cause the timing lock of the clock 116, which controls the sampling time of the analogue-to-digital converter 106, to be lost. To prevent or rectify this problem, the conventional circuit includes a thermal asperity detector 118, the output of which is fed to the digital signal processing module 110, which controls the timing recovery circuit 120. Asperity detector 118 thus detects an event that alters or destroys analogue input signal 102.
During normal operation, the digital signal processing module 110 performs phase adjustments in a timing recovery circuit 120. However, in the event that a thermal asperity is detected, the digital signal processing module 110 allows the timing recovery circuit 120 to coast over known bad areas, i.e. in effect, it does not update the phase adjustments in the timing recovery circuit 120, thereby ensuring that erroneous data does not adjust the position of the sampling point.
In the conventional circuit, however, the output from the digital signal processing module 110 is still fed to the Viterbi decoder 112 which outputs the most likely sequence of data to be input to the RLL decoder 114. Decoder 112 does not known that the data it is processing is bad data and outputs a sequence of data to the RLL decoder 114 in the usual manner. Not every sequence of bits is a valid RLL encoded sequence, and the RLL decoder 114 marks such invalid sequences as errors by setting an erasure flag to 1. The erasure flag is 0 if the sequence is a valid RLL encoded sequence.
In the prior art circuit, though, some of the data sequences output by the Viterbi decoder 112 in response to bad data are valid RLL encoded sequences (even though they are incorrect) and, as such, are not recognised as errors so no erasure flag is set. Nevertheless, as stated above, it is highly desirable for the error correction circuit (not shown) to know the location of errors, as this doubles its error correction capability.
EP-A-0926671 describes a data recovery circuit similar to the one described above, in which a thermal asperity detector is provided. The output from the RLL decoder is still output from the circuit. In addition, this output is fed into an error generation circuit, together with the output from the thermal asperity detector, and the output from the error generation circuit (which comprises an error signal indicating data sequences which are incorrect due to thermal asperity having occurred) is also output from the circuit. Thus, the arrangement described in EP-A-0926671 is an ASIC (Application Specific Integrated Circuit) having two separate outputs, one for the data itself, and one for the error signal.
In order to communicate the outputs generated by the above-described ASIC, therefore, an additional pin/line is required. However, it is highly desirable to minimise the pin count and communications lines between ASICs because:    (a) an increase in the number of pins causes a corresponding increase in size of the ASIC package, which increases its consumption of circuit board space accordingly;    (b) each pin in an ASIC requires a pad on a silicon wafer in the package, with each pad taking up space, potentially wasting silicon and increasing the price of the ASIC; thus, the above-mentioned increase in number of pins on the ASIC is for this reason undesirable;    (c) the larger the number of electrical communication lines in a package, the higher its power consumption is, which is again undesirable.
U.S. Pat. No. 5,373,513 describes a decoder for receiving and recovering encoded data. The decoder includes a peak polarity processor which senses the presence of the additive errors in the playback RLL data. The peak polarity processor classifies each additive error as either a drop-in or drop-out error and flags the affected code symbol location to the decoder as an erasure.
WO 99/18575 describes a decoder in which a thermal asperity detector is provided. When thermal asperity is detected, an event signal is fed back to activate a squelch circuit which removes large offsets caused by the thermal asperity while leaving minimal transient before the digital signal is fed to the Viterbi detector.